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| Real time clock module SERIAL-INTERFACE REAL TIME CLOCK MODULE * Builtin crystal unit allows adjustment-free efficient operation. * The small package makes high-density mounting possible. (SOP 14-pin) * Automatic calendar function (year, month, day, day of the week, hour, minute, second). * Automatic leap year correction. (up to 2099) * Builtin 30 x 4-bit S-RAM. * High-speed access. * Reference pulse output. (1024 Hz, 1/10 Hz) * Low current consumption. (1 A typical) * Similar mounting method to that used for universal type SMD IC. RTC-4553 Actual size Specifications (characteristics) Absolute Max. rating Item Supply voltage Input voltage Output voltage Storage temperature Soldering conditions Symbol VDD VIN VOUT TSTG TSOL Condition Min. Max. +6.0 -0.3 VDD+0.3 +125 V Unit VDD-GND Terminal connection 14 13 12 11 10 9 8 No. Pin terminal 1 GND 2 WR 3 SIN SCK 4 L1 5 L2 6 L3 7 No. Pin terminal 14 TPOUT 13 SOUT 12 CS1 11 CS0 10 L5 9 L4 8 VDD __ __ __ SIN,SCK, WR, CS0, CS1 ____ SOUT, TPOUT Stored without tape & reel -55 C Twice at under 260C within 10 sec. or under 230C within 3 min. 1234567 L1 to L5 are test pin. Do not connect them to any terminals. Operating range Item Operating voltage Symbol VDD -- TOPR -30 -- +70 Condition Min. 2.7 Typ. 5.0 Max. 5.5 Unit V C External dimensions (Unit: mm) Operating temperature Item Symbol f/fo Condition Ta=25C, VDD=5V AA A B Range 55 510 520 +10 -120 5 Unit Frequency tolerance ppm 10.10.2 3.20.1 Frequency voltage characteristics Aging fv fa Ta=Fix, VDD=2 to 5.5V Reference at 5V Ta=25C, VDD=5V, first year 3.1 Frequency temperature characteristics Top Ta=-10 to 70C, VDD=5V Reference at 25C 7.40.2 5.0 Frequency characteristics R4553 A E 6496 0.05 min. ppm/ year 0.6 0.15 DC characteristics VDD=5V10% (GND=OV, Ta=-30C to +70C) VDD=3V10% (GND=OV, Ta=-30C to +70C) Item Data holding voltage Symbol VDH IDD1 IDD2 VOH Condition Min. 2.0 Typ. -- Max. 5.5 100 Unit V A Item Data holding voltage Symbol VDH IDD1 Condition Min. 2.0 Typ. -- Max. 3.3 100 3.0 -- 0.4 2.0 Unit V A ___ -- ___ -- Current consumption SCK=500 kHz ___ SCK=300 kHz -- 1.0 4 VDD-0. -- -2.0 3.0 -- 0.4 2.0 -- -- 1/5 VDD 2.0 3.0 SCK=DC IOH=-400A IOL=1.6mA VOUT=5.5V VOUT=0V Current consumption IDD2 VOH ___ -- 1.0 SCK=DC IOH=-400A IOL=1.6mA VOUT=3.3V -2.0 VOUT=0V Output voltage VOL IOZH Off leak current IOZL VIH Input voltage -- VIL IIH Input current IIL Tosc VIN=5.5V -2.0 VIN=0V Ta=25C -- -- V VDD-0.4 -- Output voltage V VOL IOZH A Off leak current A IOZL VIH 4/5 VDD V 4/5 VDD -- VIN=3.3V -2.0 VIN=0V Ta=25C -- -- -- -- Input voltage VIL IIH 1/5 VDD 2.0 3.0 V A s Input current IIL Tosc A s Oscillation start-up time Oscillation start-up time 47 Real time clock module Register table Address A3 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Register symbol S1 S10 MI1 MI10 H1 H10 W D1 D10 MO1 MO10 Y1 Y10 C1 C2 C3 D3 S8 0 mi8 0 h8 PM/AM 0 d8 0 mo8 0 y8 y80 TPS BUSY SYSR D2 S4 S40 mi4 mi40 h4 0 w4 d4 0 mo4 0 y4 y40 30ADJ PONC TEST MODE 0 Counter control register D1 S2 S20 mi2 mi20 h2 h20 w2 d2 d20 mo2 0 y2 y20 CNTR -- MS1 D0 S1 S10 mi1 mi10 h1 h10 w1 d1 d10 mo1 mo10 y1 y10 24/12 MS0 Register name 1-second digit register 10-second digit register 1-minute digit register 10-minute digit register 1-hour digit register 10-hour digit register D3 RA3 RA7 RA11 RA15 RA19 RA23 RA27 RA31 RA35 RA39 RA43 RA47 RA51 RA55 RA59 MODE 1 User RAM Domain 1 D2 RA2 RA6 RA10 RA14 RA18 RA22 RA26 RA30 RA34 RA38 RA42 RA46 RA50 RA54 RA58 D1 RA1 RA5 RA9 RA13 RA17 RA21 RA25 RA29 RA33 RA37 RA41 RA45 RA49 RA53 RA57 D0 RA0 RA4 RA8 RA12 RA16 RA20 RA24 RA28 RA32 RA36 RA40 RA44 RA48 RA52 RA56 D3 RA63 RA67 RA71 RA75 RA79 RA83 RA87 RA91 RA95 RA99 RA103 RA107 RA111 RA115 RA119 MODE 2 User RAM Domain 2 D2 RA62 RA66 RA70 RA74 RA78 RA82 RA86 RA90 RA94 RA98 D1 RA61 RA65 RA69 RA73 RA77 RA81 RA85 RA89 RA93 RA97 D0 RA60 RA64 RA68 RA72 RA76 RA80 RA84 RA88 RA92 RA96 RA100 RA104 RA108 RA112 RA116 Day of the week digit register 1-day digit register 10-day digit register 1-month digit register 10-month digit register 1-year digit register 10-year digit register Control register 1 Control register 2 Control register 3 RA102 RA101 RA106 RA105 RA110 RA109 RA114 RA113 RA118 RA117 Same as MODE 0 Same as MODE 0 Note: TEST bit should be "0". Switching characteristics ___ ___ ___ ___ Item Symbol fSCK tWSCKL tWSCKH tPS tSCS tHCS tSD SCK input frequency SCK "L" time SCK "H" time SCK pause time (Ta=-30C to +70C, VDD=5V10%, GND=OV) Timing chart CS0 90% 10% Condition Min. Typ. Max. -- 500 -- 1.0 -- Unit kHz -- SCK tSCS 90% 10% t WCKL 1/f CLK t WCKH 90% t HCS __ CS0 setup time __ CS0 hold time 0 0.5 -- 0.2 1.0 0.5 150 500 SOUT s -- -- SIN 10% t SD WR 90% 10% t DSZ1 CS0 SIN data setup time SIN data Hold time tHD tSWR tHWR tDSO tDSZ1 tDSZ2 tDPZ1 tDPZ2 CL=100pF t HD ___ ___ WR setup time WR hold time SOUT delay time t SWR t HWR __ CS0, and CS1 enable to SOUT output __ CS0 disenable to SOUT high Z CS1 enable to SOUT output -- -- 100 ns t DSZ2 CS1 enable to SOUT high Z Block diagram 32.768 kHz OSC Counter Output control Day SCK Sec. Min. Hou. of Week Day Mon. Year SCK 10% t PS TPOUT Control register 1 Control register 2 Control register 3 RAM (120bit) SOUT 90% 10% t DSO SOUT SCK SIN CS1 CS0 WR Output control 90% CS1 Input control Shift register Control circuit 90% 10% 90% 10% 10% TPOUT t DPZ1 t DPZ2 48 |
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